1. Field of the Invention
The present invention relates to an information processing system including , for example, a technique for generation of instructions in an information processing system such as a microprocessor or microcontroller.
In recent years, numerous information processing systems such as CPU's (central processing units) and MPU's (microprocessing units) have been developed.
In a microcomputer housing, for example, a microprocessor or microcontroller as an information processing system, it is desired that the costs be reduced and the reliability of the product be improved moreover the maximum performance is desired to be realized with limited hardware.
2. Description of the Related Art
As will be explained later with reference to the drawings, in the conventional information processing system, when allocating a code for specific processing, for example, interrupt processing and reset processing, the practice had been to allocate unique codes to avoid overlap with user instructions. For example, two codes would be used, which could not be used by the user on an instruction map; therefore, the following problems occurred.
In normal design work, the absolute number of the instructions, which can be used by the user, is reduced by the number of instructions for the specific processing mentioned above (interrupt processing and reset processing), for example, two instructions. Therefore the efficiency of utilization of the instruction map at the user side was deteriorated.
Further, when the users differed and the codes allocated to these specific processing operations (interrupt processing and reset processing) were used, it was impossible to guarantee the operations and consequently, the possibilities of unforeseen faults increased.